Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Varanasi, 221005, India;
MOSFET; Logic gates; Leakage currents; Threshold voltage; Hot carriers; Reliability; Nanoscale devices;
机译:带有界面陷阱电荷的双栅和全栅栅MOSFET的退化模型,包括沟道移动载流子的影响
机译:界面状态产生的频道长度依赖性和氧化血管电荷的漏流雪崩热载体的HFSION / SiO_2 P沟道MOSFET的劣化,具有应变Si / SiGe通道
机译:最小化MOSFET载流子引起的热载流子氧化物电荷和界面陷阱的侧面剖析的约束
机译:用于增强热载体的双材料堆叠的异质型蓄电模式纳米管MOSFET和捕获的电荷可靠性
机译:绝缘体上硅(SOI)MOSFET的热载流子可靠性及其在非易失性存储器中的应用。
机译:具有位置载流子散射相关性的准弹道漏电流电荷和电容模型对纳米级对称DG MOSFET有效
机译:器件缩放对热载流子感应界面和MOSFET中氧化物陷阱电荷分布的影响