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A Compact Model to Predict Pillar-Edge-Roughness Effects on 3D Vertical Nanowire MOSFETs Using the Perturbation Method

机译:使用微扰方法预测3D垂直纳米线MOSFET的柱边缘粗糙度的紧凑模型

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In this paper, we present a compact model to predict the pillar-edge-roughness (PER) effects on 3D vertical nanowire MOSFETs using the perturbation method. An analytic solution to 3D Poisson's equation in the cylindrical coordinate with a perturbed boundary is obtained to describe the PER effects on the vertical channel potential. The induced variations of drain current, threshold voltage (V_(th)), and sub-threshold slope (SS) are calculated using the developed model. We also investigate the PER phase and frequency dependent behavior of the nanowire MOSFETs, and find that both phase and (angular) frequency of the PER function will significantly affect the device performance. Our model calculation results are compared with TCAD simulations and a good agreement between them is found. It is suggested that our metrology society needs to develop relevant measurement methodology to characterize the nanowire pillar-edge roughness at deep nanoscale.
机译:在本文中,我们提出了一个紧凑的模型,以使用扰动方法来预测柱边缘粗糙度(PER)对3D垂直纳米线MOSFET的影响。获得了具有扰动边界的圆柱坐标系中3D泊松方程的解析解,以描述PER对垂直通道电势的影响。使用开发的模型计算出漏极电流,阈值电压(V_(th))和亚阈值斜率(SS)引起的变化。我们还研究了纳米线MOSFET的PER相位和频率相关行为,发现PER功能的相位和(角)频率都会显着影响器件性能。将我们的模型计算结果与TCAD仿真进行比较,发现它们之间有很好的一致性。建议我们的计量学会需要开发相关的测量方法,以表征深纳米级的纳米线柱边粗糙度。

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