There is provided a method for fabricating an asymmetric vertical nanowire MOSFET (100) on a semiconductor substrate (110) comprising at least one vertical nanowire (125), comprising a core portion (120) and a shell portion (130) circumscribing the core portion (120). The method comprises depositing a protection layer (140) on the semiconductor substrate (110), forming a top contact (150) around a remaining portion (120t) of the vertical nanowire (125) not covered by the protection layer (140), removing the protection layer (140), depositing a spacer layer (160) on the semiconductor substrate (110), removing a shell portion of the intermediate portion (125i) of the bottom portion (125b) of the vertical nanowire (125), trimming a shell portion of the upper portion (125u) of the bottom portion (125b) of the vertical nanowire (125), depositing a metal gate (170) on the spacer layer (160), and forming a lower and an upper source drain portions.
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