首页> 外文会议>Design Automation Conference, 2009. ASP-DAC 2009 >A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
【24h】

A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization

机译:基于反向编码的片上AHB总线跟踪器,可有效利用循环缓冲区

获取原文

摘要

The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus, makes it difficult to reconstruct the trace from the incomplete information stored in the circular buffer. This paper proposes an efficient compression algorithm which is capable of compressing both pre-T and post-T traces. The algorithm is based on an innovative reverse encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a realtime on-chip AHB bus tracer and has been embedded in a 3D graphics SoC as an application example. The bus tracer costs only 44K gates and runs at 500MHz on 0.13um technology. Experiments have shown that this bus tracer achieves 100% circular buffer utilization and captures 1.2x and 4.86x trace depths than state-of-the-art related work and conventional industrial approaches, respectively.
机译:T后/ T前轨迹分别是指在到达目标点之前/之后捕获的轨迹。循环缓冲区中的T后跟踪的实时压缩是一个具有挑战性的问题,因为当发生回绕时,被压缩的跟踪的初始状态可能会损坏,因此很难从存储在文件中的不完整信息重建跟踪。循环缓冲区。本文提出了一种有效的压缩算法,该算法能够压缩T前和T后的迹线。该算法基于创新的反向编码方案,通过反转要编码的数据和要引用的数据的顺序。该算法已在实时片上AHB总线跟踪器中成功实现,并已作为示例嵌入到3D图形SoC中。总线跟踪器仅需花费4.4万个门,并在0.13um技术下以500MHz运行。实验表明,与最新的相关工作和常规工业方法相比,该总线跟踪器可实现100%的循环缓冲区利用率,并捕获1.2倍和4.86倍的跟踪深度。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号