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Compliant substrates with an embedded twist boundary

机译:具有嵌入式扭曲边界的兼容基板

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In this article, we propose a new model to explain how heteroepitaxial layers grown on a twist-bonded thin layer may have a significantly reduced number of threading dislocations even if the strain in the epitaxial layers is relaxed. We first point out the deficiency in the existing compliant substrate theory by showing that all the synthesized "compliant substrates" fail to behave as "ideal" free-standing templates assumed by the current theory. Our new model is constructed on the based of stress field interactions between the heteroepitaxial layer and the embedded twist boundary. In the new model, the reduction in threading dislocation density originates from the extension of the dislocation half loops due to the effect of misfit dislocation pinning by the twist boundary. When the average size of the dislocation half loops increases substantially from micrometers to millimeters or even to the size of the wafer, the density of threading dislocations drops significantly. This model does not require any "macroscopic" motion between the bonded thin layer and the handle wafer as the current theory does, which makes it more agreeable with the experimental results.
机译:在本文中,我们提出了一个新的模型来解释即使在外延层中的应变得到缓和的情况下,生长在捻接薄层上的异质外延层如何可能具有显着减少的螺纹位错数量。我们首先通过显示所有合成的“顺应性基材”都不能像当前理论所假定的“理想”独立式模板那样来指出现有顺应性基材理论的不足。我们的新模型是基于异质外延层和嵌入的扭转边界之间的应力场相互作用构建的。在新模型中,螺纹位错密度的降低源自位错半环的延伸,这是由于扭曲边界导致的错位位错钉扎的影响。当位错半环的平均尺寸从微米显着增加到毫米甚至晶片的尺寸时,穿线位错的密度显着下降。该模型不需要像当前理论那样在键合的薄层和操作晶圆之间进行任何“宏观”运动,这使其与实验结果更加吻合。

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