Effects of different processing conditions on line edge roughness for 193nm and 157nm resists

摘要

The control and minimization of resist line edge (or width) roughness (LER or LWR) is increasing in importance. It requires first a complete and reliable characterization scheme of LER, including frequency dependency, and then an investigation and understanding of its origins and methods for improvement. A new characterization method, introduced by Demokritos and based on the offline analysis of top-down SEM pictures, has been evaluated and compared to more conventional inline measurements. This enables us to include additional parameters that quantify the spatial aspects of LER, next to the classical LER 3σ value. The spatial frequency dependence can also be determined from the inline measurements. Both techniques are applied to several test cases: the impact on LER of changing softbake (SB) and post-exposure bake (PEB) temperature, and changing aerial image contrast (AIC). Also, the improvements in an etch optimization experiment are quantified. The majority of the work is concentrating on 193nm resists, but initial experiments with a 157nm resist will be shown. This work has led to a better understanding of some of the contributors to line edge roughness and gives the possibility to quantify process improvements in a better way.