A New Generalized Reconfigurable Architecture for Digital Signal Processor

机译：一种新型的通用数字信号处理器可重构体系结构

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In this paper a novel re-configurable digital signal processing (DSP) architecture and algorithm has been proposed where basic building blocks are high performance adders, subtracters, multipliers etc. The architecture has been conceived keeping high perf

机译：本文提出了一种新颖的可重配置数字信号处理（DSP）体系结构和算法，其中基本构件是高性能加法器，减法器，乘法器等。该体系结构被认为可以保持较高的性能。

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《Advanced Computing and Communications (ADCOM), 2007 15th International Conference on》|2007年|P.333-338|共6页
会议地点 Guwahati AssamIndia
作者
Basu; J.; Sahidullah; M.; Sinha; A.;
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digital signal processing chips; integrated circuit interconnections; low-power electronics; reconfigurable architectures; digital signal processor; dynamic configuration latency; generalized reconfigurable architecture; power consumption;

机译：数字信号处理芯片；集成电路互连；低功耗电子产品；可重配置架构；数字信号处理器动态配置延迟；广义的可重构体系结构；能量消耗;

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4. A New Generalized Reconfigurable Architecture for Digital Signal Processor [C] . Basu Joyanta, Sahidullah Md., Sinha Amitabha, International Conference on Advanced Computing and Communications . 2007

机译：一种用于数字信号处理器的新的广义可重新配置架构
5. A medium-grain reconfigurable architecture for digital signal processing. [D] . Myjak, Mitchell John. 2006

机译：一种中等粒度的可重配置体系结构，用于数字信号处理。
6. Flexible digital signal processing architecture for narrowband and spread-spectrum lock-in detection in multiphoton microscopy and time-resolved spectroscopy [O] . Jesse W. Wilson, Jong Kang Park, Warren S. Warren, -1

机译：灵活的数字信号处理架构用于多光子显微镜和时间分辨光谱中的窄带和扩频锁定检测
7. Dynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing Architectures [O] . N. Ramadass, S. Natarajan, J. Raja, 2008

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8. Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing [R] . Graham, P. , Nelson, B. 1999

机译：用于高性能嵌入式数字信号处理的可重配置处理器

A New Generalized Reconfigurable Architecture for Digital Signal Processor

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