A medium-grain reconfigurable architecture for digital signal processing.

摘要

Reconfigurable hardware has become an attractive option for implementing digital signal processing, especially in systems that require both high performance and flexibility. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable devices use coarse-grain cells that perform 16-bit or 32-bit operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 bits. This approach combines high flexibility with inherent support for word-length computations.; This dissertation presents a novel medium-grain reconfigurable architecture for digital signal processing. The basic cell contains an array of small lookup tables, or "elements", that operate in two modes. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements perform 4-bit arithmetic. This two-level structure offers good fine-grain flexibility without incurring the overhead of fine-grain devices.; Cells are grouped together to implement larger modules, such as multipliers, adders, and memory units. The proposed architecture features a hierarchical interconnection network that optimizes data transfer both within and between modules. Upper-level switches route data in units of words rather than bits, saving considerable area. The entire system is pipelined to maximize clock rate and throughput.; In all, the proposed architecture encompasses a large design space with many orthogonal axes. Users can control the word length, data format, amount of parallelism, and number of modules used to implement algorithms. The circuit design can also be customized to focus on a particular class of applications. For example, cells can perform computations in bit-parallel or bit-serial fashion.; Layout simulations in 180-nm CMOS technology indicate that the architecture obtains high performance. Initial prototypes have also been fabricated and tested for functionality. The estimated execution times for several common benchmarks meet or exceed the reported results of other reconfigurable devices in similar technologies.