Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures

摘要

Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a custom application-specific integrated circuit (ASIC) [1]. Recent research has shown that they are particularly appropriate for systems focused on digital signal processing (DSP) [2] and power efficiency [3]. This means that medium-grain reconfigurable architectures have a high potential for implementation in mobile computing platforms, wireless sensor networks, military technology, and aerospace applications. In mission-critical applications, it is important for MGRH architectures to avoid faults during reconfiguration. This paper focuses on the issues related to adding fault avoidance capabilities to MGRH architectures. The proposed placement algorithms have a high success rate in the order of 99% in the presence of a large number of faults (97 faulty cells).