Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

摘要

In this study, we report on the processing and the electrical characterization of a 3D-WLP TSV flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn microbump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50µm. The actual TSV and microbump process uses 3 masks, two Si-DRIE steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35µm Ø TSV, 5µm thick polymer liner, 25µm Ø Cu, 50µm deep TSV, and a 60µm TSV pitch.