Silicon Trenching Using Dry Etch Process for Back Side FIB and Probing

摘要

The proposed dry etch process has been demonstrated to be successful in backside trench preparation. Fully functional units with trenches of defined depth and location were prepared. Figure 9 shows the die substrate back side of an Intel microprocessor where multiple trenches were prepared using the proposed method. One can see that there is no limitation with respect to a non-usable zone near the die edges. Furthermore, the proposed process has comparable throughput time with respect to the LCE process. The overall time, needed for trench formation is typically 2 to 3 hours. Note that all trenches are etched simultaneously, and thus the same time is required for one trench or for several. The dry etch process method has been successfully demonstrated in preparation for backside FIB editing. The process has been used in support of FIB debug activities at Intel. Figure 10 shows the bottom of the dry etched trench where three cuts were formed using a Micrion flip chip FIB system. The success rate of the proposed method is still lower than the LCE method. The main difficulty in the process is the lack of an active endpoint detecting mechanism. Achieving desired final Si thickness currently relies on careful optical depth measurements during the the trenching process and on etch rate stability. The development of a reliable EPD can be seen as the main direction for future improvement. Trench surface quality improvement is the secondary consideration for further development. Nevertheless, even at this point in time, the dry etch trenching method has a number of advantages over the LCE method. It doesn't cause the local silicon heating which can lead to chip failure. Whereas the LCE requires special safety and environmental considerations due to the use of chlorine chemistries, this process requires no special requirements and thus it can be used in a standard lab. Finally, this methodology can serve as a reliable backup process for the LCE.