Department of Electronics Engineering, Vidyalankar Institute of Technology, Mumbai, India;
Department of Electronics Engineering, Vidyalankar Institute of Technology, Mumbai, India;
Department of Electronics Engineering, Vidyalankar Institute of Technology, Mumbai, India;
Department of Electronics Engineering, Vidyalankar Institute of Technology, Mumbai, India;
Department of Electronics Engineering, Vidyalankar Institute of Technology, Mumbai, India;
Logic gates; Adders; Transistors; MOS devices; Delays; Impedance; Simulation;
机译:在量子点元胞自动机电路的新型“多层门设计范例”中使用5输入多数门进行加法器设计
机译:DNA逻辑门设计的不同加法器电路的仿真和性能分析
机译:NML计算中多层五输入多数门和加法器/减法器电路的设计
机译:使用6TXNOR栅极设计16T完整加法器电路
机译:高速加法器和阵列乘法器的动态电流模式逻辑电路的分析和设计。
机译:全光学设计固有节能的可逆门和电路
机译:可逆TsG门的设计与仿真高效加法器电路的应用