【24h】

Design of 16T full adder circuit using 6TXNOR gates

机译:使用6TXNOR门设计16T全加法器电路

获取原文
获取原文并翻译 | 示例

摘要

Adders are most useful circuits for processor and microcontroller designs such as multipliers, shifters and other complex VLSI applications. This paper proposes design of 16T-one bit full adder circuit comprising of XNOR gates, pass transistors and transmission gate logic. The design includes two 6T XNOR gates and one 2:1 MUX. Functionality of the design is faithfully verified using Cadence Virtuoso Simulation tool using GPDK 180nm technology. The W/L ratio of 2μm/180nm is considered for all the transistors. The performance of 16T single bit Full Adder has been investigated and evaluated by the simulation results obtained from the improved design of XNOR gate and has resulted in improvement of power dissipation and output voltage.
机译:加法器对于处理器和微控制器设计(例如乘法器,移位器和其他复杂的VLSI应用)最有用的电路。本文提出了由XNOR门,传输晶体管和传输门逻辑组成的16T一位全加法器电路的设计。该设计包括两个6T XNOR门和一个2:1 MUX。使用GPDK 180nm技术的Cadence Virtuoso Simulation工具可以如实地验证设计的功能。所有晶体管的W / L比均为2μm/ 180nm。通过对XNOR门的改进设计获得的仿真结果对16T单比特全加器的性能进行了研究和评估,从而改善了功耗和输出电压。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号