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Design of 16T full adder circuit using 6TXNOR gates

机译:使用6TXNOR栅极设计16T完整加法器电路

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摘要

Adders are most useful circuits for processor and microcontroller designs such as multipliers, shifters and other complex VLSI applications. This paper proposes design of 16T-one bit full adder circuit comprising of XNOR gates, pass transistors and transmission gate logic. The design includes two 6T XNOR gates and one 2:1 MUX. Functionality of the design is faithfully verified using Cadence Virtuoso Simulation tool using GPDK 180nm technology. The W/L ratio of 2μm/180nm is considered for all the transistors. The performance of 16T single bit Full Adder has been investigated and evaluated by the simulation results obtained from the improved design of XNOR gate and has resulted in improvement of power dissipation and output voltage.
机译:加法器是处理器和微控制器设计的最有用电路,如乘数,移位器和其他复杂的VLSI应用程序。本文提出了16T-ONE全加法电路的设计,包括Xnor栅极,通过晶体管和传输门逻辑。该设计包括两个6T Xnor栅极和一个2:1 mux。使用GPDK 180NM技术使用Cadence Virtuoso仿真工具忠实地验证设计的功能。所有晶体管都考虑了2μm/ 180nm的w / l比。通过从Xnor栅极的改进设计获得的模拟结果研究和评估了16T单位完整加法器的性能,并导致了提高了功率耗散和输出电压。

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