A power efficient phase frequency detector and low mismatch charge pump in on-chip clock generator

摘要

In this manuscript, we propose a robust on-chip clock generator circuit using a power efficient phase frequency detector and a low current mismatch dual adaptive regulated cascode charge pump in 180nm UMC MPW RF process. The proposed PFD uses only 20 transistors and is free from dead zone. It consumes a power of 5.4μW for an input reference frequency of 50MHz and can support a maximum frequency of 2.5GHz at PLL output. The proposed charge pump limits the variation in charging and discharging currents to 0.09% of its biasing value, which is designed to be 182.5μA, for change in control voltage from 0.4V to 1.2V. This reduces the jitter to less than 2ps at the PLL output frequency of 2.3GHz. The charge pump avoids operational amplifiers in its design, resulting in lesser a rea and power without any loss in functionality.