BIST is one of the DFT techniques in which the test circuitry will be present along with the CUT. Different BIST architectures are proposed in order to reduce the area overhead, power overhead, test time and test costs. The STUMPS architecture is best suited for BIST environment in terms of area and power, but it requires external TPG and Compactor. This paper presents the modified low power STUMPS architecture which eliminates the need for external TPG, by modifying one of the scan chains to operate in both scan and TPG mode. The proposed architecture is tested by considering 16×16 multiplier as CUT and results shows that area overhead is reduced by 4.4 % when compared to STUMPS architecture.
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