Area and power efficient 4-bit comparator design by using 1-bit full adder module

摘要

In this paper an area and power efficient 56T 4-bit comparator design has been presented by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 PMOS. A GDI full adder module has been used to design this comparator which consumes less area and power at 120 nm as compared to previous full adder designs. The proposed 4-bit comparator design is based on this area and power efficient 10T full adder module. To get area and power efficiency a centralized full adder module has been used which avoid cascade implementation of XOR module to get sum and carry output. Full adder modules outputs have been used for the generation of output of 4-bit comparator designs. The proposed 4-bit GDI comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power and current variation with respect to the supply voltage has been performed on BSIM-4 using 120nm technology. Results show that Area of proposed 4-bit comparator design is 1320.3μm on 120nm technology. At 1.2V input supply voltage the proposed 4-bit GDI comparator consumes 13.739μW power at BSIM-4. At 1.2V proposed GDI 4-bit comparator has shown improvement of 6.3% in terms of area and 69.42% in power as compared to the PTL 4- bit comparator.