1-BIT ADDER AND MULTIPLIER CONTAINING A 1-BIT ADDER

摘要

E.g. for video applications fast multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough. The inventive multiplier in nearly full CMOS design has been constructed with a 1.2 ν BICMOS technology, having a multiplication time of 9 ns with a supply voltage of 5 volts. Minimum multiplication time has been achieved by a combination of the following techniques: use of the Booth-Mc Sorley algorithm in order to reduce the number of partial products; diagonal propagation of the carry from one partial product to the other allowing all the sums on one line to be done simultaneously; use of the carry select approach in the final 14 bits adder and in the first two adders in the intermediate rows; use of inventive fast one-bit full adders with complementary pass transistor logic.