A novel FPGA design of modified residue to binary converter for three moduli set

摘要

This paper proposes a novel modified reverse converter for the unrestricted moduli set. This uses to investigate the Residue Number System (RNS) to decimal equivalent binary conversion for the utilization of RNS numbers in Digital Signal Processing (DSP) applications. First, we simplify the Chinese Remainder Theorem in order to obtain a reverse converter that uses mod-(2n−1) operations. Next, we further analyze the theorem for the low complexity implementation that does not require the explicit use of modulo operation in the conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. The proposed converter is implemented on Xilinx Spartan 3 field-programmable gate array. The results indicate that the proposal shows the better performance in conversion time, area cost and power consumption.