An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs

摘要

A comprehensive Chip LIfetime Predictor (CLIP) macro for automatically characterizing gate dielectric failure reduces the stress time and silicon area by a factor proportional to the number of FETs to be tested. A flexible DUT cell that can be stressed in isolation without thicker tox FETs to 4 times supply voltage, enables accurate lifetime prediction under different ON and OFF state dielectric breakdown modes for both low voltage core and high voltage IO devices.