This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-µm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 µm×120 µm.
展开▼
