An low-power clocking interface for next-generation high-speed DRR6/7 applications

摘要

A low-power clocking interface for next-generation high-speed DRR6/7 applications is presented. The low-power clocking interface for the next-generation high-speed DRR6/7 application proposed in the present invention receives an asynchronous low-speed clock input from the CPU, a low-power clocking interface including an additional clock buffer for a high-speed synchronous clock system, and receives the clock from the low-power clocking interface. , receiving clocks from H-tree-based clock distribution networks and H-tree-based clock distribution networks having a symmetric structure, and using a plurality of DRAMs each including a Phase-Locked-Loop (PLL) and ILFM. include