首页> 外文会议>2006 7th International Conference on Electronics Packaging Technology(ICEPT 2006) >Electroless Plating Ni-based Barrier Layers for Silicon Vertical Interconnects
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Electroless Plating Ni-based Barrier Layers for Silicon Vertical Interconnects

机译:用于硅垂直互连的化学镀镍基阻挡层

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摘要

A novel fabrication process for electroless plating NiMoP barrier layer on SiO_2 was presented for 3D packaging with silicon vertical interconnects. The NiMoP film was deposited electrolessly by using a silane coupling agent as an adhesion and catalyzed layer. In addition, a potential NiMoP barrier/seed layer was successfully formed via electroless plating atop SiO_2 after Pd activation. The composition and the electrical resisitivity of NiMoP were investigated by scanning electron microscope (SEM) and four-point probe. The barrier layer and seed layer functions of NiMoP were verified by direct Cu electroplating and Auger electron microscope (AES).
机译:提出了一种新的在SiO_2上化学镀NiMoP势垒层的制造工艺,该工艺用于具有硅垂直互连的3D封装。通过使用硅烷偶联剂作为粘附和催化层化学沉积NiMoP膜。此外,在Pd活化后,通过在SiO_2顶部化学镀成功形成了潜在的NiMoP势垒/种子层。通过扫描电子显微镜(SEM)和四点探针研究了NiMoP的组成和电阻率。通过直接铜电镀和俄歇电子显微镜(AES)验证了NiMoP的阻挡层和种子层功能。

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