3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking

摘要

It is clear that the further evolution of microelectronic technology and electronics systems will increasingly requirire 3D interconnect technologies. Depending on the applications different 3D-interconnect densities will be required. In this paper we have listed a number of 3D technologies (3D-SIP 3D-WLP, 3D-SIC) that can be deal with these different densities in a cost effective way. Further, we have focused on the realization of 3D-WLP through-Si vias. IMEC has developed a new approach of making 3D through-Si vias a potential lower cost and with improved electrical and thermon mechnical performance by using partial Cu plating process and conformal polymer dielectric coating.