A LITHOGRAPHY-BASED COMPLIANT CHIP-TO-SUBSTRATE WAFER-LEVEL INTERCONNECT

摘要

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next- generation packaging, β-fiy is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill, β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication ofβ-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading ofβ-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.