Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects

摘要

Compliant chip-to-substrate "G-Helix" interconnects have been fabricated using electroplating and sequential lithography. Wafer-level, lead-free solder attachment, no-underfill processing, reworkability, large-area processing, scalability, and fine-pitch are some of the highlights of these interconnects. In this paper the assembly of such compliant interconnects on an organic substrate is presented. Results from mechanical compliance tests are also presented. The robustness of the compliant interconnects is also demonstrated through mechanical loading. An integrative system solution is presented where a combination of compliant interconnects and column interconnects is used to optimize the mechanical and electrical performance.