Architectural design and process for manufacturing monolithic integrated 3D CMOS logic and memory

摘要

Semiconductor devices are provided. The device includes a plurality of transistor pairs stacked on the substrate. Each of the plurality of transistor pairs includes an n-type transistor and a p-type transistor stacked on top of each other. The device also includes a plurality of gate electrodes stacked on the substrate in a staircase configuration. The plurality of gate electrodes are electrically connected to the gate structure of the plurality of transistor pairs. The device further includes multiple source / drain (S / D) local interconnects stacked on the board in a staircase configuration. The plurality of S / D local interconnects are electrically coupled to the source and drain regions of the plurality of transistor pairs.