首页>
外国专利>
ARCHITECTURE DESIGN AND PROCESSES FOR MANUFACTURING MONOLITHICALLY INTEGRATED 3D CMOS LOGIC AND MEMORY
ARCHITECTURE DESIGN AND PROCESSES FOR MANUFACTURING MONOLITHICALLY INTEGRATED 3D CMOS LOGIC AND MEMORY
展开▼
机译:用于单芯片集成的3D CMOS逻辑和内存制造的体系结构设计和过程
展开▼
页面导航
摘要
著录项
相似文献
摘要
A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.
展开▼