An SRAM cell includes: first, second, third, fourth, and fifth dielectric fins disposed in this order along a first direction and oriented lengthwise along a second direction, where the first and the fifth dielectric fins define two edges of the SRAM cell; a first N-type semiconductor fin disposed between the first and the second dielectric fins; a second N-type semiconductor fin disposed between the fourth and the fifth dielectric fins; a first P-type semiconductor fin disposed between the second and the third dielectric fins; a second P-type semiconductor fin disposed between the third and the fourth dielectric fins, where each of the first and the second N-type semiconductor fins and each of the first and the second P-type semiconductor fins is oriented lengthwise along the second direction; and gate structures oriented lengthwise along the first direction, where the gate structures engage one or more of the dielectric fin.
展开▼
