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Superjunction semiconductor device and manufacturing method of superjunction semiconductor device

机译:超结半导体器件和超结半导体器件的制造方法

摘要

Problem to be solved: to provide an ultra junction semiconductor device capable of reducing an ion implantation step for forming a base region and a method of manufacturing an ultra junction semiconductor device.The super junction semiconductor device comprises a silicon carbide semiconductor substrate 1 of a first conductivity type, a first semiconductor layer 2 of a first conductivity type, a first trench 30 provided in the first semiconductor layer 2, a bottom surface continuous to an opening of the first trench 30, opening in the upper surface of the first semiconductor layer 2, and a first Torre A second trench 31 having a width wider than that of the knee 30 is provided.The third semiconductor region 6 of the second conductivity type is provided inside the first trench 30, and the second semiconductor region 3 of the second conductivity type is provided inside the second trench 31.A fifth semiconductor region 7 having a higher impurity concentration than the third semiconductor region 6 is provided in the third semiconductor region 6.A gate trench 18 extends through the third semiconductor region 6 and the fifth semiconductor region 7 to reach the first semiconductor layer 2.Diagram
机译:要解决的问题:提供一种能够减少用于形成基部区域的离子注入步骤的超结半导体器件和制造超结半导体器件的方法。超结半导体器件包括第一导电类型的碳化硅半导体衬底1,第一导电类型的第一半导体层2,设置在第一半导体层2中的第一沟槽30,底表面连续到开口第一沟槽30,在第一半导体层2的上表面中开口,以及具有比膝关节30的宽度宽的宽度的第一托管第二沟槽31。在内部提供第二导电类型的第三半导体区域6第二导电类型的第一沟槽30和第二半导体区域3设置在第二沟槽31.A中,在第三半导体区域6A中设置了具有比第三半导体区域6更高的杂质浓度的第五半导体区域7栅极沟槽18延伸穿过第三半导体区域6和第五半导体区域7以到达第一半导体层2.DiaGram

著录项

  • 公开/公告号JP2021040042A

    专利类型

  • 公开/公告日2021-03-11

    原文格式PDF

  • 申请/专利权人 富士電機株式会社;

    申请/专利号JP20190160534

  • 发明设计人 藤澤 広幸;

    申请日2019-09-03

  • 分类号H01L29/78;H01L29/12;H01L21/336;H01L29/739;

  • 国家 JP

  • 入库时间 2022-08-24 17:40:01

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