Circuit arrangement for the data exchange between the central and peripheral devices

摘要

1459621 Automatic exchange systems; master and slave systems SIEMENS AG 11 April 1974 [30 May 1973] 16114/74 Headings H4K and H4P In a computer controlled exchange having a common data bus via which a set of peripherals R may intercommunicate with each other or with a central processor C, the latter cyclically addresses the peripherals so as to communicate therewith whereas an independent cyclical address unit H addresses the peripherals during pauses in central processor addressing so as to permit inter-peripheral communication. The peripherals may be register buffers each of which serves a set of telephone relay sets. Every address emitted by the processor is accompanied by a transmit or receive instruction bit while every address emitted by the address unit is accompanied by an invitation to transmit bit. The peripherals respond by indicating that they have nothing to transmit or that they are not ready to receive, by sending data to the processor with an indication of the total number of data words that they are going to use or by sending the address of a register with which they wish to communicate. Each register recognizes its own address and responds automatically.