Method of manufacture of devices a semi - power conductors of a grid isolee

摘要

Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein source 62 and base 64 regions and a source-to- base ohmic short 69 are formed employing self-aligned techniques are disclosed. The processes begin with a semiconductor wafer, a gate insulating layer initially formed on the surface of the wafer, and a polysilicon gate layer. Through masking and etching steps, channels are etched through the polysilicon gate layer to the wafer. The unetched portions define polysilicon gate electrodes spaced along the wafer. An initial etch produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form the source-to-base short 69. In a subsequent etch, previously unetched portions of the polysilicon gate electrode layer are etched to define wider channels and insulated polysilicon gate electrode structures 70 spaced along the wafer surface. MOSFET source 62 and base 64 regions are then formed, employing the polysilicon gate electrode structures as masks. IMAGE