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Electronic circuit capable of carrying out a succession of divisions at a high speed without an objectionable error

机译:能够高速连续进行除法的电子电路

摘要

The electronic circuit for dividing a dividend (RR) by a divisor (RD) calculates an eventual quotient (Q). An approximate reciprocal (RC) of the divisor is read out of a memory (34) and multiplied in a first multiplication circuit (36) by the divisor to obtain a correction factor (C1). A second multiplication circuit (37) multiplies the dividend by the approximate reciprocal to calculate a first provisional quotient. This is processed by a first adder circuit (61) and a first partial divider (641). The first partial provisional quotient (P1) is modified into the first partial quotient (Q1) with reference to the second provisional quotient in a first correction circuit (661). Likewise, an i-th partial quotient (Q1) is successively produced from an i-th correction circuit (661) by modifying an i-th partial provisional quotient (Pi) with reference to an (i + 1)-th provisional quotient. The first through the N-th partial quotients (Q1, Q2....QN) are synchronously produced as the eventual quotient (Q) from a synchronization circuit (105). The electronic circuit is capable for carrying out a division at a high speed.
机译:用于将除数(RR)除以除数(RD)的电子电路计算出最终商(Q)。从存储器(34)中读出除数的近似倒数(RC),并在第一乘法电路(36)中除以该除数,以获得校正因子(C 1 )。第二乘法电路(37)将除数与近似倒数相乘以计算第一临时商。这由第一加法器电路(61)和第一部分除法器(64 1 )处理。参照第一校正电路中的第二临时商(66 1 )修改为第一部分商(Q 1 ) > 1 )。同样地,通过修改第i个部分临时商(i),从第i个校正电路(66 1 )相继产生第i个部分商(Q 1 )。 P i )关于第(i +1)个临时商。从同步电路(105)将第一至第N部分商(Q 1 ,Q2 .... QN)作为最终商(Q)同步产生。该电子电路能够高速执行分割。

著录项

  • 公开/公告号EP0154182A3

    专利类型

  • 公开/公告日1986-06-11

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP19850101228

  • 发明设计人 KANAZAWA TAKASHI;

    申请日1985-02-06

  • 分类号G06F7/49;G06F7/52;

  • 国家 EP

  • 入库时间 2022-08-22 07:35:43

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