Method of power raising in Galois fields GF(2n) for data processing, protection and transmission, etc., in particular for key selection in encrypted data transmission, and circuits for carrying out such a method

摘要

The arrangement comprises a control logic (C) for generating loading clock pulses or control clock pulses (T1 ... T4); memories (S1, S2, S3, S4) are connected directly or indirectly with signal outputs to the control logic (C) in such a way that the control logic (C), from the output signals of the memories (S1 ... S4), emits control clock pulses (T1 ... T4) in a different, pre-determined way, the control clock pulses (T1 ... T4) are sent in a predetermined manner to signal inputs of the memories (S1 ... S4) and of a processing unit (SM) arranged between the third memory (S3) and the fourth memory (S4). The signal outputs of the fourth memory (S4) are sent solely to signal inputs of the processing unit (SM) and the signal outputs of the third memory (S3) are sent both to signal inputs of the processing unit (SM) and to signal inputs of the control logic (C). IMAGE