Buffered FET logic gate using depletion-mode MESFET's.

摘要

A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (V.sub.I); and thereby a high load drivability with a low power consumption rate is realized.