An integrated circuit with a memory, comprising a matrix of memory cells and sense amplifiers which are coupled thereto, the inputs of the sense amplifiers being connected to one another, the outputs of the sense amplifiers being connected to one another via a read bus. During the reading of inforamtion from a memory cell, the sense amplifiers are simultaneously activated. As a result, the access time for reading information from a a memory cell remains substantially constant when the number of memory columns to be connected in parallel is changed. The dimensioning of the sense amplifiers may remain the same when the number of memory columns is changed, so that dimensioning need be performed only once. This results in a saving as regards time and costs.
展开▼
