首页> 外国专利> HIGH-SPEED LOGIC LSI

HIGH-SPEED LOGIC LSI

机译:高速逻辑LSI

摘要

PURPOSE: To make a high-speed logic LSI versatile by expanding the use field of a high-speed LSI by enabling the input/output of low-speed parallel data for the LSI provided with a logic processing part to be operated at high speed in a bit serial state concerning the high-speed logic LSI enabling the input/output of high-speed serial data and low-speed parallel data. ;CONSTITUTION: A logic processing part 1 for logically processing the high-speed serial data of a frequency (f) and outputting the processing result as high-speed serial data, P/S conversion part 3 for converting the low-speed parallel input data composed of parallel (n) bits at a frequency f/n to the high-speed serial data, selector 2 for selecting the serial input data and serial data from the P/S conversion part 3 based on a mode switching signal and inputting the selected data to the logic processing part 1, an S/P conversion part 4 for converting the high-speed serial data outputted from the logic processing part 1 to the low-speed parallel output data composed of parallel (n) bits at the frequency f/n are provided on the same LSI clip.;COPYRIGHT: (C)1994,JPO&Japio
机译:用途:通过使具有逻辑处理部分的LSI的低速并行数据的输入/输出能够高速运行,从而扩展高速LSI的使用领域,从而使高速逻辑LSI变得通用。与高速逻辑LSI有关的位串行状态,允许输入/输出高速串行数据和低速并行数据。 ;组成:逻辑处理部分1,用于对频率(f)的高速串行数据进行逻辑处理,并将处理结果作为高速串行数据输出,P / S转换部分3,用于转换低速并行输入数据选择器2,由与高速串行数据的频率为f / n的并行(n)位组成,选择器2用于基于模式切换信号选择串行输入数据和来自P / S转换部分3的串行数据并输入所选择的S / P转换部分4将从逻辑处理部分1输出的高速串行数据转换为由频率为f /的并行(n)位组成的低速并行输出数据。 n提供在同一LSI剪辑上。版权所有:(C)1994,JPO&Japio

著录项

  • 公开/公告号JPH06103025A

    专利类型

  • 公开/公告日1994-04-15

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19920248472

  • 发明设计人 TSUNODA NOBUYUKI;

    申请日1992-09-18

  • 分类号G06F5/00;H03K19/0175;

  • 国家 JP

  • 入库时间 2022-08-22 04:52:23

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号