Logic dividing procedure for allocation of logic circuits to a module having several LSIs, requires generating dividing results of logic device electronic circuit using logic used by an external interface signal

摘要

In logic dividing procedures for arranging logic circuits into a module with several programmable large-scale integration circuits (LSIs) problems arise concerning the housing sizes, the connection structure and the connection pins reference list which can change in a module having programmed LSIs under development and working logic circuits. Problems concerning dividing paths having critical delay into segments also occur and to avoid such short-comings the logic dividing procedure now initially involves storing information having a reference between at least one connector for signals reception from the programmable logic devices and for sending signals to these devices and external interface signals, and with the information read via the connections between the connectors and the programmable logic devices. The dividing results of the logic device's electronic circuit are then generated with the first logic, which the external interface signal uses, being assigne d to the programmable logic device connected via a line directly to one of the connectors assigned to the external interface signal.