0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-system

摘要

0.1-/spl mu/m CMOS devices for high speed logic and system LSIs have been successfully achieved. The device has an SiO/SiN stacked gate dielectric with T/sub oxinv/=2.8 nm to avoid gate direct tunneling leakage and boron penetration. It also utilizes a poly/metal stacked gate electrode to reduce gate resistance. Carefully optimized source/drain extensions and punch-through stoppers offer good short channel operation below 0.1-/spl mu/m gate length and high-drive currents of 1000 /spl mu/A//spl mu/m for NMOSs and 410 /spl mu/A//spl mu/m for PMOSs at 1.5 V voltage supply.