首页> 外国专利> integrated halbleiterschaltungsanordnung with a group of logical circuits and a group of ram memory.

integrated halbleiterschaltungsanordnung with a group of logical circuits and a group of ram memory.

机译:集成halbleiterschaltungsanordnung,具有一组逻辑电路和一组ram内存。

摘要

A semiconductor integrated circuit device has a logic macro (21) and RAM macros (221, 222), and each RAM macro has a plurality of latch circuits, an operation circuit (32) and a memory cell array (31). At least one of outputs of the latch circuits within the RAM macro is coupled to the operation circuit thereof by a first interconnection (34a) when the RAM macro is used. When the RAM macro is not used, all of the outputs of the latch circuits are coupled to certain internal cells (25) of the logic macro by a second interconnection (34b-34e). The first and second interconnections are determined by a function to be carried out in the circuit device, that is, designed by CAD, for example, depending on the kind or model of the circuit device.
机译:半导体集成电路器件具有逻辑宏(21)和RAM宏(221、222),并且每个RAM宏具有多个锁存电路,运算电路(32)和存储单元阵列(31)。当使用RAM宏时,RAM宏内的锁存电路的输出中的至少一个通过第一互连(34a)耦合到其操作电路。当不使用RAM宏时,锁存电路的所有输出通过第二互连(34b-34e)耦合到逻辑宏的某些内部单元(25)。第一和第二互连由要在电路装置中执行的功能来确定,即由CAD设计,例如,取决于电路装置的种类或型号。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号