patsuke - ji null for semiconductor integrated circuit

摘要

PURPOSE:To enable easily the failure obstacle analysis of a semiconductor integrated circuit after cap sealing, from the outside, by arranging exposed check-pattern-measuring-terminals outside a forming region of external connection lead if a package for a semiconductor integrated circuit. CONSTITUTION:A plurality of metallized patterns 7 for check pattern are formed, on the edge portions of four sides of outer peripheral part on the mounting surface of semiconductor integrated circuit of a substrate 1a except the forming region of a metallized pattern 9 on the substrate 1a. A plurality of exposed check-pattern measuring-terminals 8 are formed in the recessed parts arranged on the outer peripheral part of the bottom part of the substrate 1a. Each of the metallized patterns 7 and each of the check pattern- measuringterminals 8 are connected via a through hole 10 so as to correspond with each other. By using the exposed check-pattern-measuringterminals 8, a check pattern formed on the semiconductor integrated circuit in which basic elements such as a transistor and a resistor and the similar ones are patternized, can be measured from the outside.