DIGITAL CLOCK DEJITTER CIRCUITS FOR REGENERATING CLOCK SIGNALS WITH MINIMAL JITTER.

摘要

the digital circuit includes a clock stabilization of ram (20) for receiving an incoming signal (14), a space fractional digital full vacuum calibration memory (30) for the continuation of the average rates of entry into and exit from the mem r - and to obtain an indication of sequential controla digital frequency generator (40) is adjustable to receive a clock signal and the control indication, and for providing a clock signal therefore essentially stabilized at the same rate as the incoming signal space design.the calibration device of full memory (30) consists of a meter reading, writing (54) and (56) are the movement of incoming and outgoing data from the memory, and a soustracteur (58) in the difference value per meter in the depths of memory.the digital frequency generator (40) is adjustable to an adder (72), a register (74) and a clock divider (fcc) (76), which provides a digital display device for calibrating fractional deep memory.