Semiconductor static random access memory devices that terminate disturbance testing in short time spans

摘要

The semiconductor static random access memory device is subjected to a disturbance test before being delivered to the customer to ensure the data retention capability of the memory cell. A mode signal (MODE) higher than the standard voltage range causes the disturbance test to be executed Thereby causing the block address decoder unit 15 to simultaneously drive the plurality of column address decoder units 14a-14d, thereby reducing the time period for disturbance testing.