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Heterojunction FET with a high potential barrier layer and gate structure

机译:具有高势垒层和栅极结构的异质结FET

摘要

A field effect semiconductor device which restricts current flow through a drain-gate path, but allows current to easily flow through a gate-source path. A high potential barrier layer is formed on the drain side of an active layer. The potential barrier layer has a wider energy band gap than the active layer. A source electrode and a drain electrode make ohmic contact with the active layer and a gate electrode exists between the source electrode and the drain electrode. The gate electrode is partially formed on the potential barrier layer and makes Schottky contact with the active layer on the source side of the semiconductor device and makes Schottky contact with the potential barrier layer on the drain side of the semiconductor device.
机译:一种场效应半导体器件,其限制电流流过漏极-栅极路径,但允许电流容易地流过栅极-源极路径。高电位势垒层形成在有源层的漏极侧。势垒层具有比有源层宽的能带隙。源电极和漏电极与有源层欧姆接触,并且栅电极存在于源电极和漏电极之间。栅电极部分地形成在势垒层上,并且与半导体器件的源极侧上的有源层肖特基接触,并且与半导体器件的漏极侧上的势垒层肖特基接触。

著录项

  • 公开/公告号US5399886A

    专利类型

  • 公开/公告日1995-03-21

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19940186466

  • 发明设计人 YUUICHI HASEGAWA;

    申请日1994-01-26

  • 分类号H01L29/784;H01L29/804;H01L29/812;

  • 国家 US

  • 入库时间 2022-08-22 04:05:18

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