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FET contg. potential barriers - has source-drain regions on substrate, gate electrode on insulation layer, channel region between substrate, source-drain and semiconductor layers
FET contg. potential barriers - has source-drain regions on substrate, gate electrode on insulation layer, channel region between substrate, source-drain and semiconductor layers
FET has a pair of source/drain regions (5) on a main substrate surface, an insulation layer (6) formed on the main surface, a gate electrode (9) on the insulation layer surface, a channel region (7) formed in the substrate between the pair of source/drain regions, and spaced first and second semiconductor layers (2) which have a bandgap wider than that of the silicon in the channel region and which inhibit majority carrier movement between the pair of source and drain regions. Processes for prodn. of the FET are also claimed. ADVANTAGE - The FET exhibits a large resonant quantum tunnel effect and is simple and inexpensive to mfr.
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