A semiconductor memory integrated circuit with a possibility for masking of the writing in the memory.

摘要

PURPOSE:To reduce the arrangement area and to reduce the size of a device by connecting write amplifier enable signal lines and write mask data lines in series through write mask decoders. CONSTITUTION:The above semiconductor memory is equipped with a memory cell array S1, write amplifiers 111 - 114 which write data in the memory cell array S1, write data lines WD1 - WD4 which are connected to the write amplifiers 111 - 114 and supply write data, and write amplifier enable signal lines E1 - E4 which are connected to the write amplifiers 111 - 114 and activate the write amplifiers 111 - 114. Then receiving means 41 - 44 receive write mask data for bit-by-bit write mask specification at the time of multi-bit input/output mode constitution from outside and a supply means 90 is connected to receiving means 41 - 44 and the write enable signal lines E1 - E4 to supply write mask data to the write enable signal lines E1 - E4. Consequently, the number of input signal lines to the write amplifiers can be decreased, the arrangement area is reducible, and the size of the device can be reduced.