Multiple phase shifted clocks generation using a minimal set of signals from a PLL

摘要

An inventive apparatus for generating a plurality of phase- shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock and a reference voltage, local clock generation circuit disposed at a second location, and a first conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference clock from the PLL to the local clock generation circuit. The inventive apparatus further includes a second conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference voltage from the PLL to the local clock generation circuit; wherein the plurality of phase-shifted clocks are generated at the second location, responsive to the reference voltage and the reference clock, using the local clock generation circuit.