Over sampling rotary frequency detector especially for PLL in telecommunication system - has phase scanner receiving input and reference clock signals generating first phase signal which indicates input clock signal on one flank of reference clock signal

摘要

The detector includes a first phase scanner which receives an input signal and a reference clock signal and generates a first phase signal. The generated first phase signal indicates the input clock signal on at least one flank of the reference clock signal, with the scanner containing a specified phase scanning rate. The reference clock signal is received by a phase correction generator which generates a phase fault signal, with the phase fault comprising specified parameters. The first phase and phase fault signals are fed to a phase subtractor which generates a phase difference signal, indicating the respective phase difference. The phase difference signal is received by a phase and frequency detector which provides a sign output signal and a heterodynamic signal of specified parameters.