Circuit for generating clock signals for phase locked loops compares signals at reference signal input and second end of second delay path, outputs second clock signal depending on comparison

摘要

The circuit has a reference signal input and 2 clock signal outputs. A first delay path is connected at a first end to the reference signal input and at the second to the first clock signal output. A second delay path is connected at a first end to the first delay path's second end. A comparator outputs the second clock signal depending on a comparison of the signals at the reference signal input and at the second end of the second delay path. The circuit generates first and second clock signals from one input signal, whereby the first and second clock signals are shifted relative to each other by a defined phase angle. It has a reference signal input (1) and first and second clock signal outputs (2,3). A first delay path (4) is connected at a first end to the reference signal input and at the second end to the first clock signal output. A second delay path (5) is connected at a first end to the second end of the first delay path. A comparator (7) for comparing the signals at the reference signal input and at the second end of the second delay path outputs the second clock signal depending on the comparison.