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Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof
Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof
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机译:包括受图案化氮化物钝化保护的CMOS器件的集成电路结构及其制造方法
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摘要
A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.
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