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Logic circuit with the function of controlling discharge current on pull- down and emitter coupled logic circuit

机译:具有控制下拉和发射极耦合逻辑电路上的放电电流的逻辑电路

摘要

A first current switch circuit 1a outputs a first logic signal and a complementary signal thereof in response to an input logic signal. A pull- up transistor Q10 has a base receiving the first logic signal. A second current switch circuit 1b outputs a second logic signal based on the complementary signal and the potential of an output terminal OUT1. A level shift circuit 1c shifts the level of the second logic signal and provides it to the base of a pull-down transistor Q11. When the potential of an input terminal IN1 changes from a low level to a high level, a capacitive load CL is discharged through transistors Q9 and Q11. When the potential of output terminal OUT1 becomes lower than that of a first reference potential terminal VBB1, the second logic signal attains a low level, thereby turning off pull-down transistor Q11.
机译:第一电流开关电路1a响应于输入逻辑信号而输出第一逻辑信号及其互补信号。上拉晶体管Q10的基极接收第一逻辑信号。第二电流开关电路1b基于互补信号和输出端子OUT1的电位来输出第二逻辑信号。电平移位电路1c对第二逻辑信号的电平进行移位,并将其提供给下拉晶体管Q11的基极。当输入端子IN1的电位从低电平改变为高电平时,电容性负载CL通过晶体管Q9和Q11放电。当输出端子OUT1的电位变得低于第一基准电位端子VBB1的电位时,第二逻辑信号变为低电平,从而使下拉晶体管Q11截止。

著录项

  • 公开/公告号US5572152A

    专利类型

  • 公开/公告日1996-11-05

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI KABUSHIKI KAISHA;

    申请/专利号US19950573604

  • 发明设计人 KIMIO UEDA;

    申请日1995-12-15

  • 分类号H03K19/20;

  • 国家 US

  • 入库时间 2022-08-22 03:37:38

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